| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 93 | Implementation of Aging-Aware Multiplier Design for Area and Power Critical Applications Authors:BOWRISETTI SPANDANA, G. ASWAN KUMAR |
0474-0478 |
Download | |
| IJVDCS 94 | A Study on Implementing Novel Adder in HEVC DCT to Achieve Area And Power Efficiency Authors:SHANIBA K.K, VEENA K |
0479-0481 |
Download | |
| IJVDCS 95 | A Novel Approach to Implement Scalable DCT Architecture for Timing Critical Applications Authors:MUDIDANA VENKATESH, V. KEERTHI KIRAN |
0482-0488 |
Download | |
| IJVDCS 96 | Fault Tolerant Parallel Reconfigurable FIR Filters in VHDL Authors:NIMMY THOMAS, SUVITHA P. S |
0489-0491 |
Download | |
| IJVDCS 97 | VLSI Implementation of Power and Timing Optimized Fixed-Point Circuits Authors:SETTI JYOTHISREE, B. V. R. GOWRI |
0492-0496 |
Download | |
| IJVDCS 98 | Implementation of Low Error And Area Efficient Fixed Width Multiplier by using Minor Input Correction Vector Authors:RONGALI SIREESHA, P. ASHOK KUMAR |
0497-0500 |
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| IJVDCS 99 | Critical Path- Analysis and Low - Complexity Implementation of the LMS Adaptive Algorithm Authors:D. SESHAVENI, N. G. N. PRASAD |
0501-0505 |
Download | |
| IJVDCS 100 | Power Optimized Implementation of Fault Tolerant Parallel Filters Authors:SAGIREDDI C S DURGA VARAPRASAD, P.K. SURESH |
0506-0510 |
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| IJVDCS 101 | Implementation of Low Power Resolution Algorithm for Common Sub Expression Elimination in Digital Filter Design Authors:NAGULAPALLI SURESH, G.V.K.S PRASAD |
0511-0514 |
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| IJVDCS 102 | Low Power Implementation of Data Flow Transformation of Carry Save Representation in Arithmetic Circuits Authors:MADDIPATI MOUNIKA, T. GANGADHARA RAO |
0515-0519 |
Download | |
